Memory controller

ABSTRACT

A memory controller includes a terminal to receive, from a processor, a request for access to a dynamic random access memory having a data storage area divided into a plurality of banks each divided into a plurality of pages. A memory control unit is also provided to activate a page to be accessed, based on said access request from said processor, and to execute, before a next request for access to a page to be accessed subsequently by said processor, precharge of said page to be accessed subsequently.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a memory controller, or inparticular to a memory controller suitable for accessing a dynamicrandom access memory (DRAM) for storing image data or the like.

[0002] In recent years, with rapid extension of ownership of personalcomputers or the like, an increased number of DRAMs have been suppliedas a main memory of the personal computers. At the same time, the priceof the DRAM has decreased to such an extent that it has come to beemployed also for an electronic equipment other than personal computers.The DRAM includes a synchronous DRAM (hereinafter referred to as SDRAM)which can be continuously written into and read from at higher speed insynchronism with the clock of an interface (hereinafter referred to asthe burst transfer), a double data rate SDRAM (hereinafter referred toas DDR-SDRAM) having a burst transfer increased to a double speed byexecuting the burst transfer of the SDRAM in synchronism with both theleading edge and the trailing edge of the clock signal, and a RambusDRAM (hereinafter referred to as RDRAM). Of these DRAMs, SDRAM canconstitute an inexpensive, large-capacity memory, and therefore has cometo be employed by more and more equipment. The SDRAM also has come to beused in place of the conventional expensive dedicated memory (VRAM) as aframe memory for temporarily holding the image data displayed on adisplay unit. The SDRAM are regulated by JEDEC Standard 21-C.

[0003] Examples of devices for accessing image data of the SDRAM includea display processing device for reading and transferring image data to adisplay unit and a graphic processing device for generating graphicsdata and writing them as image data to draw arbitrary graphics. Theimage data generated by a video input device can also be written andstored in the SDRAM. Further, a SDRAM can be configured as a unifiedmemory in which a main memory and a frame memory for storing image dataare integrated into a single memory. With an SDRAM configured as aunified memory, not only image data but also instruction codes andvarious data are accessed by processors, and therefore an efficientmemory access is required.

[0004] In storing image data in a frame memory, the image data isassigned to a two-dimensional address space which is finite inhorizontal and vertical directions in order to hold the image data in adata storage area. The image data are held as an arrangement inhorizontal and vertical directions corresponding to a display screen(display pixels) of a display device. The image data of each pixelcorresponding to the display screen is configured of several to severaltens of bits, and the bit length of the image data of one pixel isdetermined by the data format.

[0005] In storing image data in the SDRAM as a frame memory, on theother hand, the data storage area is divided into a plurality of, sayfour, banks, each of which is in turn divided into several pages, andeach page is assigned a row address. In setting an address in the framememory having this configuration, the linear address mapping and thetile address mapping are employed.

[0006] The linear address mapping is a method in which assuming that ahorizontal arrangement of pixel data is a line, the pixel data arrangedin horizontal direction (image data corresponding to the pixels of thedisplay screen arranged in horizontal direction) are assignedhorizontally continuous addresses and all the display pixels in a lineare assigned the same row address, i.e. the row address of the samepage. In this case, the pixel data of a different line is assigned adifferent row address of the same bank, or the row address of adifferent bank. In other words, the pixel data of a different line areassigned a different page.

[0007] The tile address mapping, on the other hand, is a method in whichthe pixel data in a rectangle (hereinafter referred to as the tile)having 32 bytes in horizontal direction and 16 lines in verticaldirection are assigned continuous addresses, and all the pixel data ineach tile are assigned the same row address, i.e. the same page. In thiscase, the pixel data (image data) of a different tile are assigned adifferent row address of the same bank, or the row address of adifferent bank. In other words, the pixel data of a different tile areassigned a different page.

[0008] The SDRAM requires the refresh operation for holding data, and inaccessing the SDRAM, the page to be accessed is designated by a rowaddress, and all the data belonging to the designated page are activatedby being transferred to and amplified by a sense amplifier. Of the datathus activated, only the data designated by a column address areaccessed by the read or write operation. In this case, the data of thesame page can be continuously accessed. For different pages, however,all the data in the sense amplifier are required to be precharged bybeing returned to the original page, after which all the data belongingto the page to be accessed are activated by being transferred to andamplified by a sense amplifier.

[0009] In this way, the data belonging to the same page can becontinuously accessed, and therefore the access efficiency can beimproved. When accessing a different page, however, a page mishitoccurs. In this case, the page to be accessed is precharged andactivated before being accessed, resulting in a lower memory accessefficiency. In accessing the SDRAM, therefore, a page mishit isdesirably reduced, and in setting the address mapping in the SDRAM, therequirements of the device functions must be met.

[0010] Specifically, assume an application of the linear address mappingto the SDRAM used for a display processing device. In view of the factthat the display processing device makes access in one direction eitherfrom left to right or from right to left on a line, a page mishit is notcaused and can be suppressed as long as the same line is being accessed.In an application of the tile address mapping to the SDRAM used for thedisplay processing device, however, a page mishit is often caused. Thisis by reason of the fact that the display processing device can startaccess with an arbitrary address, and the scroll of the image displayedand the boundaries of a plurality of display image planes (hereinafterreferred to as the planes) are set at arbitrary positions. An accessfrom the display processing device to the pixel data continuous along aline of the SDRAM using the tile address mapping, therefore, goes overthe tile boundary (the boundary between tiles). Thus, a page mishitoccurs each time a tile boundary is crossed, resulting in a reducedmemory access efficiency.

[0011] In the case where a graphic processing device accesses the SDRAMusing the linear address mapping, in contrast, the continuous access ispossible and the page mishit can be reduced for horizontal drawing. Inthe case of vertical or diagonal plotting, however, a different page isaccessed for each cycle, and therefore a page mishit occurs for eachdrawing cycle, thereby reducing the memory access efficiency.

[0012] Specifically, the graphic processing device is adapted togenerate arbitrary graphics in accordance with a draw instruction codegiven and write the image data on the generated graphics in atwo-dimensional address space of. the SDRAM. Also, the graphics drawnare configured of straight lines and curves of arbitrary angles.Therefore, the addresses to be accessed are continuous in horizontaldirection, in vertical direction or in diagonal direction. As a result,as long as the tile address mapping is set in the SDRAM used for thegraphic processing device, a page mishit occurs only when crossing atile boundary regardless of the direction of access, horizontal,vertical or diagonal. It is therefore possible to reduce the page mishitmore than when using the linear address mapping. For this reason, thetile address mapping is more preferable for the graphic processing, andmany equipment with a frame memory realized by the SDRAM employ the tileaddress mapping.

[0013] A sort of real time operation is required for reading image databy the display processing device. Specifically, unless the readoperation of the image data is completed within a predetermined time,the image displayed on the display unit comes to flicker. For preventingthe image flicker, the arbitration of accesses to the SDRAM is importantas well as improving image data access efficiency by suppressing thepage mishit of the SDRAM. Especially, the unified memory configurationoften causes the contention between the access from the graphicprocessing device and the accesses-from other devices such asprocessors. Therefore, how to suppress the delay of image data accessdue to the access contention is crucial.

[0014] A method for accessing a SDRAM efficiently as a frame memory isproposed in JP-A-8-255107. In this method, the address to be accessed iscompared with the address of the preceding access to decide on a pagehit. In the case where a page mishit occurs. the bank is precharged anda new page is activated. Then, the write or read operation is executed.In the case of a page hit, on the other hand, the write or readoperation is executed immediately without bank precharge or pageactivation. Further, an address counter is included which is incrementedsuccessively by a predetermined unit count. Thus, it is possible for thedisplay processing device to read the image data efficiently bysuspending access to a given page immediately before access to adifferent page when the different page is to be accessed while the givenpage is being continuously accessed.

[0015] In JP-A-8-255107, however, the address to be accessed and theaddress of the preceding access are simply compared with each other forpage hit decision of the SDRAM. Therefore, the interleave access to aplurality of banks (a method of distributing the accesses to a pluralityof banks to improve the access efficiency by individual activation ofthe pages of each of two or four banks) which is the feature of theSDRAM cannot be utilized for improving the access efficiency.

[0016] Also, according to JP-A-8-255107, for reading the image data bythe display processing device, in the case where a different page isaccessed while the data of a given page are being continuously accessed,a page mishit is prevented by suspending the ongoing access. Whenexecuting the succeeding access, however, a page mishit occurs afterall, and therefore the precharge and the activation of the banks are notavoidable.

[0017] Further, JP-A-8-255107 fails to take into consideration thearbitration to meet the requirement for the real time operation by thedisplay processing device in the case where a plurality of accessescompete with each other.

SUMMARY OF THE INVENTION

[0018] The object of the present invention is to provide a memorycontroller making possible efficient access to a dynamic random accessmemory.

[0019] In order to achieve the object described above, according to thepresent invention, there is provided a memory controller comprisingmeans for receiving a request for accessing a dynamic random accessmemory having a data storage area divided into a plurality of banks eachdivided into a plurality of pages, and memory control means foractivating the page to be accessed, based on the access request and,before executing the access to the activated page, executing the advanceprecharge of the page to be accessed subsequently.

[0020] In the memory controller according to this invention, afteractivation of the page to be accessed and before accessing the activatedpage, the. bank or the page to be accessed next or subsequently isprecharged in advance. When accessing the bank or the page to beaccessed next or subsequently, therefore, the particular bank or thepage, as the case may be, is not required to be precharged and can beaccessed by the read or write operation after activation withoutprecharge. Even in the case where a different page is accessed due to apage mishit, therefore, the time is saved after precharge to activation.Thus, the time overhead can be shortened and an efficient access can beachieved. As a result, the data amount accessible per unit time can beincreased thereby contributing to an improved band width.

[0021] On the other hand, assume that while an access request from agiven processor unit is selected and under execution, an access requestof higher priority, e.g. an access request of higher requirement forreal time operation is newly input and access requests from a pluralityof processor units (devices) contend each other. The access based on theselected access request is suspended, and the newly input access requestis given priority of access. Even in the case where a plurality ofaccess requests contend each other, therefore, an access request ofhigher priority (access request of higher requirement for real timeoperation) can be executed in priority, thereby suppressing the accessdelay for image data which otherwise might be caused by the contentionbetween access requests.

[0022] In the case where the advance precharge is not conducted, on theother hand, the status of the dynamic random access memory is managed insuch a manner that an access is executed in accordance with the statusof the memory. Therefore, the memory can be accessed positively inaccordance with the memory status. Further, in the case where theadvance precharge is not conducted and a page mishit is caused, theprecharge and activation are carried out within the shortest timing inkeeping with the minimum cycles between activation and precharge and theminimum cycles between precharge and activation by reference to theinformation on the active flag, the row address buffer RAS counter andthe RP counter.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023]FIG. 1 is a diagram showing a block configuration of an imageprocessing system employing a memory controller according to thisinvention.

[0024]FIG. 2 shows a configuration for explaining the linear addressmapping of image data.

[0025]FIG. 3 shows a configuration for explaining the tile addressmapping of image data.

[0026]FIG. 4 is a block diagram showing a memory controller according tothis invention.

[0027]FIG. 5 is a diagram showing a block configuration of an accessarbiter.

[0028]FIG. 6 is a diagram showing an example of the setting of the moderegister of the access arbiter.

[0029]FIG. 7 is a configuration diagram for explaining the order ofpriority in the access arbiter.

[0030]FIG. 8 is a time chart for explaining the operation of the accessarbiter.

[0031]FIG. 9 is a time chart for explaining the operation of the accessarbiter.

[0032]FIG. 10 is a time chart for explaining the operation of the accessarbiter.

[0033]FIG. 11 is a diagram showing a block configuration of an bankmanagement and address generator.

[0034]FIG. 12 is a diagram showing an example of address generation inthe address generator.

[0035]FIG. 13 is a block diagram showing a bank status management unit.

[0036]FIG. 14 is a block diagram showing a memory control unit.

[0037]FIG. 15 shows a state transition for controlling the command issuein the command generator.

[0038]FIG. 16 is a diagram for explaining the state transitionconditions for controlling the command issue in the command generator.

[0039]FIG. 17 is a diagram for explaining the output signal state due tothe status transition for controlling the command issue in the commandgenerator.

[0040]FIG. 18 is a diagram for explaining an example of generation of abyte enable signal in a DQM generator.

[0041]FIG. 19 is a block diagram showing a read data control unit.

[0042]FIG. 20 is a block diagram showing a data control unit.

[0043]FIG. 21 is a time chart for memory access in the case where theadvance precharge is not carried out in the memory controller accordingto this invention.

[0044]FIG. 22 is a time chart for memory access in the case where theadvance precharge is carried out in the memory controller according tothis invention.

DESCRIPTION OF THE EMBODIMENTS

[0045] An embodiment of the invention will be explained below withreference to the accompanying drawings. FIG. 1 is a diagram showing asystem configuration for application of a memory controller according tothe invention to an image processing system. In FIG. 1, the imageprocessing system is a graphics card built in a personal computer or acar navigation system mounted on an automobile, for example, andcomprises a memory controller 1, a plurality of processing units and asingle memory.

[0046] The plurality of the processing units include a processor(hereinafter referred to as the CPU) 2 for executing the sequenceprocessing and data processing, a graphic processing unit (hereinafterreferred to as the RU) 3 for executing a two-dimensional or athree-dimensional graphic processing, a display processing unit(hereinafter referred to as the DU) 4 for transferring the display imagedata to a display unit 81, a video processing unit (hereinafter referredto as the BU) 5 for retrieving video image data from a video camera unit82 and an input/output control unit (hereinafter referred to as the IOU)6 for controlling data transfer to and from the peripheral equipmentsuch as an external storage unit 83 and a communication unit 84. Amemory 7 shared by all these units is configured of a SDRAM. The memory7 may alternatively be a double data rate (DDR) DRAM capable of fasteraccess than the SDRAM.

[0047] The memory (dynamic random access memory) 7 has a data storagearea divided into, for example, a plurality of banks, each of which inturn is divided into a plurality of pages, and each page is assigned toa bank different from that for adjacent pages. Each page of the memory 7has stored therein the instruction codes and data processed in the CPU2, the draw instruction codes and the graphic data processed in the RU3, the display image data read from the DU 4 and the video image datawritten from the VU 5. The instruction codes and the data are written orread by the-peripheral equipment through the IOU 6.

[0048] The system configuration can be implemented with a single LSI byintegrating the memory controller 1, the RU 3, the DU 4, the VU 5 andthe IOU 6. The CPU 2 may also be added to and integrated with thesecomponent parts to implement a single LSI. Further, the memory 7 may beadded to realize a single LSI. The processing units including the CPU 2,the RU 3, the DU 4, the VU 5 and the IOU 6 by which the memory isaccessed will hereinafter be referred to as the devices by way ofexplanation.

[0049] The memory controller 1, upon receipt of access requests from thedevices, arbitrates them for selecting one of the access requests,generates a command based on the selected access request, and executesthe read or write operation (access) for the memory 7 in accordance withthe command. Specifically, the memory controller 1 comprises an accessarbiter 10, a memory control unit 11, a bank management and addressgenerator 12, a multiplexer (hereinafter referred to as the MUX) 14 anda data control unit 15.

[0050] The access arbiter 10, upon receipt of access requests from aplurality of devices which contend each other, is adapted to determinethe order in which the memory is accessed, based on a predeterminedpriority order. The memory control unit 11 generates a command based onthe access request from a device determined by the access arbiter 10,and thus controls the operation of reading from or writing into thememory 7 in accordance with a control signal based on the particularcommand. In this case, since the memory 7 presupposes a SDRAM, thecontrol operation is performed in accordance with the read and writesequence of the SDRAM. The bank management and address generator 12,upon receipt of the command from the memory control unit 11, manages thestatus of the memory 7 in accordance with the command, and at the sametime, in order to select a bank and a page to be accessed based on theaccess request from the device selected by the access arbiter 10,generates a bank address, a row address and a column address, holds theinformation required to optimize the access to the memory 7 and outputsthe information thus held to the memory control unit 11. The MUX 14selects the address and the data of the device selected by the accessarbiter 10, and outputs the selected data to the bank management andaddress generator 12, etc. The data control unit 15 is adapted totemporarily hold the data to be written into the memory 7 or the dataread from the memory 7.

[0051] To the address space of the memory 7, there is allocated ahorizontally and vertically finite two-dimensional address space to holdthe graphic data, the display image data and the video image data. Thegraphic data, the display image data and the video image data are eachconfigured of several bits or several tens of bits per pixel. Thesedata, when stored in the memory 7, are aligned in horizontal andvertical directions in the same manner as if a corresponding image isdisplayed on the screen of the display unit. The bit length of data ofone pixel is determined by the data format.

[0052] In storing the graphic data, the display image data and the videoimage data in the memory 7, the linear address mapping method or thetile address mapping method can be employed. In the case where thelinear address mapping method is employed by dividing the memory 7 intofour banks (bank addresses 0 to 3) and dividing each bank into n pages,for example, as shown in FIG. 2, each line is allocated to a page,horizontally continuous addresses are allocated to each line, and thepixel data in each line are allocated to the same row address, i.e. thesame page. To each line, however, there is allocated a different rowaddress of the same bank or a row address of a different bank.Specifically, each line is allocated with a different page. In thiscase, the column addresses (0 to 511) correspond to the pixels of thescreen, respectively.

[0053] In the case where the tile address mapping method is employed bydividing the memory 7 into four banks; on the other hand, as shown inFIG. 3, each page is set as a rectangle (hereinafter referred to as thetile) having 32 bytes in horizontal direction and 16 lines. in verticaldirection. Each tile is allocated with continuous addresses (0 to 511),and all the pixel data in each tile are allocated to the same rowaddress, i.e. the same page. Each tile, however, is allocated with adifferent row address of the same bank or a row address of a differentbank. In other words, each tile is allocated to a page of a differentaddress from adjacent tiles.

[0054] In employing the linear address mapping method or the tileaddress mapping method, it is necessary to take the functions of eachdevice into consideration.

[0055] The RU 3, for example, is adapted to generate arbitrary graphicsin accordance with a draw instruction code and write the graphics intothe two-dimensional address space of the memory 7. Since the graphicsdrawn are configured of straight lines and curves of an arbitrary angle,the addresses to be accessed are continuous in horizontal, vertical ordiagonal direction. In the linear address mapping, therefore, continuousaccess is possible for horizontal drawing, but the vertical or diagonaldrawing requires the access to a different page of the memory 7 for eachcycle, so that a page mishit occurs for each cycle, thereby leading to alower memory access efficiency.

[0056] In the case where the tile address mapping method shown in FIG. 3is employed, on the other hand, a page mishit is caused only when thetile boundary is crossed regardless of whether the access is horizontal,vertical or diagonal. For the graphic processing, therefore, the tileaddress mapping shown in FIG. 3 is desirably employed.

[0057] The display image data are read from the memory 7 by the DU 4 andthe video image data are written into the memory 7 by the VU 5 under apredetermined rule. Specifically, both devices are adapted to access thememory 7 along a line continuously in one direction, either from left toright or from right to left. The address to start the access with,however, is arbitrary. This is attributable to the scroll of the displayimage, or the control operation of the transfer data buffer in the DU 4or the VU 5. In the case where the tile address mapping is employed forthe DU 4 and the VU 5 and the continuous access along a line over thetile boundary is requested, therefore, a page mishit occurs each timethe tile boundary is crossed. Unless the access is efficient at the timeof a page mishit, the memory access efficiency is deteriorated.

[0058] The operation of reading the display image data by the DU 4 orthe operation of writing the video image data by the VU 5, on the otherhand, requires a sort of the real time processing. Specifically, unlessthe display image data are completely read within a predetermined lengthof time, the image displayed on the display unit flickers. In the casewhere the video image data are not completely written within apredetermined length of time, on the other hand, the video imagedisplayed on the display unit becomes temporarily still. For accessingthe memory 7, therefore, it is crucial not only to improve the accessefficiency of the display image data and the video image data bysuppressing the effect of a page mishit but also to arbitrate the accessrequests from the devices as well.

[0059] Especially in the case where the memory 7 is shared by thedevices as a unified memory, the access requests from the devicesfrequently contend each other, and therefore it is crucial. how tosuppress the access delay of the display image data and the video imagedata which may be caused by the access request contention.

[0060] For this reason, the memory controller 1 according to thisembodiment is so configured as not only to perform the processing forsuppressing the effect of a page mishit but also to perform theprocessing for suppressing the access delay of the display image dataand the video image data in case of contention of accesses from aplurality of devices. For this purpose, the memory controller 1, asshown in FIG. 4, is supplied with various signals from the devicesthrough interfaces. The memory controller 1 and the devices areconnected to each other through independent interfaces, respectively,which have the same specification. Each interface is implemented withthe following signals, where i (=a . . . ,e) is an identifier of eachdevice.

[0061] The access arbiter 10, as shown in FIG. 4, is supplied with aready signal (RDYi), a write/read discrimination signal WRi and a lastcycle discrimination signal ENDi from each device, and an acknowledgesignal (ACKi) is output from the access arbiter 10 to each device. TheMUX 14 is supplied from each device with a byte enable signal BEi[3:0],an access destination address ADRi[25:2] and write data WDTi[31:0]. Onthe other hand, a read data strobe signal RSTBi is output from thememory control unit 11 to each device, and the data control unit 15outputs read data RDTi[31:0] to each device. Further, the memorycontroller 1 and the memory 7 are connected to each other through aSSDRAM interface. Thus, the memory control unit 11 outputs to the memory7 the control signals for designating a command, including a chip selectsignal CS#, a row address strobe signal RAS#, a column address strobesignal CAS#, a write enable signal WE# and a data mask signal DQM[3:0]for masking specific data. Also, the bank management and addressgenerating unit 12 outputs to the memory 7 a bank address BA[1:0] and arow/column address A[12:0] for selecting the bank and the page to beaccessed, and the read/write data DQ[31:0] are exchanged between thedata control unit 15 and the memory 7. Character # designates a signalof negative logic. In this embodiment, only the signals required forexplanation are described.

[0062] A signal indicating a memory read access or a memory write accessis output from each device to the memory controller 1 as an accessrequest in synchronism with a clock, as shown in FIG. 21. In this case,the memory access is executed in units of four bytes equal to the datawidth. The cycle in which the 4-byte memory access is executed is calledan access cycle. The shortest access cycle is one clock cycle, but mayrequire 2 or more clock cycles in the case where the devices contendeach other or depending on the activation or precharge of the banks ofthe memory 7. The transmission and receipt of the memory access address(also including the write data and the byte enable signal in the case ofthe write access) are executed independently of the transmission andreceipt of the read data. Without waiting for the return of the readdata, therefore, the next access request can be accepted. Each device,when issuing a memory access request, asserts the read signal RDYi (tohigh level of “1”), while at the same time outputting the first accessaddress ADRi. In the case where the access length is not more than 4bytes, the first access cycle is the last access cycle, and thereforethe last cycle discrimination signal ENDi is also asserted with the readsignal RDYi. In the case of the write access, the ready signal RDYi isasserted while at the same time asserting the write/read discriminationsignal WRi. Also, the first write data WDTi and the byte enable signalBEi are output. In the case of the read access, on the other hand, theready signal RDYi is asserted, while at the same time negating thewrite/read discrimination signal WRi (to low level of “0”). In the caseof the read access, neither the write data WDTi nor the byte enablesignal BEi is required to be output.

[0063] The memory controller 1, upon detection of the assertion of theready signals RDYi from the devices, selects by arbitration-an accessfrom one of the plurality of the devices, and retrieves the address ADRiof the destination of the particular access. In the case where theread/write discrimination signal WRi is asserted, the write data WDTiand the byte enable signal BEi are also retrieved. An acknowledge signalACKi is asserted for the selected device. The acknowledge signal ACKi isasserted, in the shortest case, within the same clock cycle as the onein which the assertion of the ready signal RDYi is started. As describedabove, however, the assertion of the acknowledge signal ACKi may bedelayed one or more clock cycles due to the contention with otherdevices or depending on the activation or precharge of the banks of thememory 7. In such a case, the devices hold the output status of eachsignal until the acknowledge signal ACKi is asserted. Once the deviceacknowledge signal ACKi is asserted, the next address ADRi is outputwith the ready signal RDYi asserted in the next clock cycle (Al). Thisis also the case with the signals WRi, WDTi and BEi. The access addressADRi may not be continuous with the preceding address value. Also, inthe last access cycle, the last cycle discrimination signal ENDi is alsoasserted.

[0064] The memory controller 1 accepts the last access cycle (assertsthe acknowledge signal ACKi) for which the last cycle discriminationsignal ENDi is asserted. At the same time, the memory controller 1, upondetection of the assertion of the ready signal RDYi of another device,makes arbitration and can accept the access cycle of the particulardevice in the next clock cycle. The device of which the last accesscycle has been accepted is not arbitrated. Nevertheless, such a devicecan immediately issue the next access request by asserting the readysignal RDYi.

[0065] The memory controller 1, when it selects the access from onedevice, basically accepts only the access of the same device until theassertion of the last cycle discrimination signal ENDi. The period fromthe selection of the access of a given device by the memory controller 1to the acceptance of the last access cycle (the assertion of theacknowledge signal ACKi) for which the last cycle discrimination signalENDi has been asserted is called a transaction. The addresses of aplurality of the access cycles executed during one transaction arearbitrary, and addresses can be accessed over a plurality of pagesduring one transaction period. Each device can negate the ready signalRDYi and thereby temporarily stops the memory access during the periodof one transaction. Also, both a read access and a write access can berequested together during the period of one transaction. Since theefficiency of memory access is adversely affected, however, such accessrequests are desirably issued after provisional termination of theongoing transaction by asserting the last cycle discrimination signalENDi.

[0066] The access arbiter 10 will be specifically described withreference to FIGS. 5 to 10. The access arbiter 10, as shown in FIG. 5,includes a mode register 100, a device selector 101 and a counter 102,and a register bus REGBUS is connected to each device.

[0067] The mode register 100 sets the order of priority for memoryaccess arbitration, the column latency of the memory 7 (the number ofclock cycles from the issue of a read command for the SDRAM to theoutput of the read data from the SDRAM) and the precharge mode. The dataon the column latency and the order of priority are set in the moderegister 100 through the register bus REGBUS.

[0068] As shown in FIG. 6, the order of priority PRi[2:0] of memoryaccess of each device, the column latency CL2, and the precharge modePDi indicating whether the advance precharge is executed or not inresponse to a request from each device are set in the mode register 100.Two or three cycles are set as the column latency, so that the columnlatency is 3 cycles in the case-where CL2 is 0, and the column latencyis 2 cycles in the case where CL2 is 1. In the case where PDi is 0, onthe other hand, it indicates that the advance precharge is not executedfor the particular device, while in the case where PDi is 1, itindicates that the advance precharge is executed in response to therequest from the particular device.

[0069] As to the order of priority PRi[2:0]=“000” to “111”, as shown inFIG. 7, the smaller the value of PRi[2:0], the higher the order ofpriority. In the case where the same order of priority is set for aplurality of devices, the accesses from the devices are arbitratedaccording to the round robin algorithm. Specifically, in the arbitrationaccording to the round robin algorithm, a device from which the accesshas been accepted at a time point nearest to the timing of execution ofarbitration has the lowest order of priority among the devices initiallyhaving the same order of priority. In the case where the order ofpriority is “000”, the privilege mode prevails. In the case where adevice set to the privilege mode issues a memory access request, thetransactions in execution for the other devices are suspended (notsuspended in the case where the transaction in execution is in privilegemode), and the transaction of the device in privilege mode is executedignoring the ABORT signal from the counter 102 described later.

[0070] The device selector 101, upon detection of the assertion of theready signals RDYi from the devices, asserts the ready signals RDY,selects a device in accordance with the order of priority set in themode register 100 and holds the signal for discriminating the particulardevice. At the same time, the device selector 101 outputs the number ofthe device as DEVSEL[3:0] and the write/read discrimination signal WRiof the selected device as WR. In the case where the advance prechargePDi of the selected device is set to 1 in the mode register 100, thedevice selector 101 asserts the advance precharge signal PDEV. Theassertion of RDY and the output of DEVSEL[3:0], WR and PDi are sustainedduring the period when RDYi of the selected device is asserted.

[0071] Also, the device selector 101, upon detection of the assertion ofthe acknowledge signal ACK from the memory control unit 11, asserts theacknowledge signal ACKi for the selected device. In the case where theselected device asserts the last cycle discrimination signal ENDi in thesame cycle, the device selector 101 determines that the transaction isover, and asserts the END signal for one clock cycle in the counter 102while at the same time restarting the arbitration of accesses in thenext clock cycle.

[0072] The counter 102 clears the count upon assertion of the last cyclediscrimination signal END signal, and during the assertion of theacknowledge signal ACK, sequentially increments the count in synchronismwith the clock cycle. When the count value comes to coincide with apredetermined set value, the counter 102 asserts the ABORT signal.Specifically, the counter 102 is for counting the number of accesscycles for a given transaction. In the case where the number of accesscycles of the transaction of a given device is extremely long, thememory access from other devices is adversely affected. Therefore, anupper limit is set for the number of access cycles per transaction, inthe case where the counter 102 detects that the upper limit of thenumber of access cycles has been reached, the memory controller 1provisionally suspends the transaction (which is called the abort), andaccepts the memory access of another device. The upper limit of thenumber of access cycles per transaction can be set to an arbitrary valueon the counter 102 through the register bus REGBUS.

[0073] The device selector 101, upon detection of the assertion of theABORT signal of the counter 102, determines that the transaction issuspended, and asserts the END signal for one clock cycle on the counter102 while at the same time restarting the arbitration of accesses fromthe next clock cycle. The devices cannot recognize the suspension of thememory access by the abort, and recognize it as a simple delay of theassertion of the acknowledge signal ACKi by the memory controller 1. Thedevices, therefore, continue the assertion of the ready signal RDYi. Inthis way, the memory controller 1 selects and continues to execute thesuspended transaction based on the order of priority immediately aftercompletion of the next or subsequent transaction.

[0074] Now, the operation of the access arbiter 10 will be explainedwith reference to FIGS. 8 to 10. FIG. 8 shows the case in which thedevice a is in write access and the number of access cycles is 2, whilethe device b is in read access and the number of access cycle is 1, theorder of priority being higher for the device a than for b. The value ofDEVSEL[3:0] is 0001 for the device a and 0010 for the device b.

[0075] In FIG. 8, in the case where the device a and the device b assertthe ready signal RDYi at the same time at clock cycle T0, the memorycontrol unit 11 selects the device a based on the order of priority. Thememory control unit 11 asserts the acknowledge signal ACK for the firstaccess cycle of the device a at the clock cycle T2, and asserts theacknowledge signal ACK for the next access cycle at the clock cycle T3.Further, after the assertion of the last cycle discrimination signalENDa at the clock cycle T3, the device-b is selected from the clockcycle T4 and the read access is executed. At the clock cycle T8, theacknowledge signal ACK is asserted for the first and last access cyclefor the device b.

[0076] On the other hand, assume that the transaction for the device ais suspended by the abort signal. As shown in FIG. 9, the transactionfor the device a is started at clock cycle T0, and suspended by theassertion of the ABORT signal at clock cycle T3. The transaction for thedevice b is executed at the next clock cycle T4. Since the number ofaccess cycle of the transaction for the device b is 1, the transactionfor the device b is terminated at clock cycle T4, and the transactionfor the device a is restarted from the next clock cycle T5.

[0077] Suppose that a memory access requests comes from the device b inprivilege mode while the transaction for the device a is underexecution. As shown in FIG. 10, the transaction for the device a, whichis started at clock cycle T0, is suspended at clock cycle T3 when theready signal RDYi is asserted by the device b in privilege mode, and thetransaction for the device b is executed at the next clock cycle T4. Thetransaction for the device b, of which the number of access cycle is 1,is terminated at clock cycle T4 and the transaction for the device a isrestarted from the next clock cycle T5.

[0078] A configuration of the bank management and address generatingunit 12 is shown in FIG. 11. The bank management and address generatingunit 12 includes an address generating unit 120, a bank statusmanagement unit 121, a bank address latch 140 and a row/column addresslatch 141. The address generating unit 120 and the bank statusmanagement unit 121 are supplied with various commands generated by thememory control unit 11, and the address generating unit 120 is suppliedwith an access address ADR[25:2] and a mode signal CONF[3:0].

[0079] An active command ATCISS is applied to the memory 7 from thememory control unit 11 as a signal indicating that an active command hasbeen issued, and a precharge command PREISS is applied to the memory 7from the memory control unit 11 as a signal indicating that a prechargecommand has been issued. Also, an advance precharge command PPREISS isapplied from the memory control unit 11 to the memory 7 as a signalindicating that an advance precharge command has been issued in advanceprecharge mode. An all-bank precharge command PALLISS, on the otherhand, is applied to the memory 7 from the memory control unit 11 as asignal indicating that a precharge command for executing the prechargeof all the banks has been issued, and a mode register set command MRSISSis applied as a signal indicating that a mode register set command hasbeen issued.

[0080] The address generating unit 120 generates and outputs a bankaddress BADR[1:0], a row address RA[12:0], a row address or a columnaddress MADR[12:0] based on the access address ADR[25:2] indicating theaddress of a device selected by the MUX 14, the mode signal CONF[3:0]indicating the configuration (memory capacity) of the memory-7 andvarious commands. Whether MADR[12:0] is a row address or a columnaddress is determined by the type of the command issued. The signalBA[1:0] (=“00” to “11”) for selecting one of the four banks representsthe bank address BADR[1:0] latched by a latch 140, and the row/columnaddress A[12:0] represents the address MADR[12:0] latched by a latch141. Specifically, the address generating unit 120 outputs, as anelement of the memory control means, the bank address BA[1:0] and therow/column address A[12:0] for selecting a bank to be accessed among thebanks of the memory 7, a page and specific data in the page.

[0081] The bank status management unit 121 holds the status of each bankof the memory 7 based on the various commands issued from the memorycontrol unit 11, and supplies the memory control unit 11 with theinformation for optimizing the access to the memory 7. Specifically, thebank status management unit 121 holds the following bank statusinformation by bank:

[0082] (1) Whether in active or inactive state

[0083] (2) Column address in active state

[0084] (3) Whether the minimum number of cycles between activation andprecharge has passed

[0085] (4) Whether the minimum number of cycles between precharge andactivation has passed.

[0086] Based on these information, the bank status management unit 121supplies the memory control unit 11 with the following information foreach access cycle:

[0087] (1) BACT: indicating that the bank to be accessed is active.

[0088] (2) PHIT: indicating that the page to be accessed is active (pagehit).

[0089] (3) IRAS: indicating that the minimum number of cycles has passedin the process from activation to precharge in the bank to be accessed.

[0090] (4) IRP: indicating that the minimum number of cycles has passedin the process from precharge to activation in the bank to be accessed.

[0091] (5) IRASALL: indicating that the minimum number of cycles haspassed in the process from activation to precharge in a bank.

[0092] These information are supplied to the memory control unit 11 as ahigh-level signal, for example.

[0093] The address generating unit 120 generates various addresses inaccordance with the configuration (memory capacity) of the memory 7 asshown in FIG. 12. The mode signal CONF[3:0] shows a configuration of thememory 7. In the case where CONF[3:0] is “0”, the memory 7 has fourbanks (banks 0 to 3) each 4096 pages, while each having 2567 words perpage. In the case where the CONF[3:0] is “1”, on the other hand, thememory 7 is configured of four banks each having 4096 pages which inturn each contains 512 words. Further, in the case where CONF[3:0] is“2”, the memory 7 is configured of four banks each having 8119 pageswhich in turn contains 512 words. One word is 32 bits (4 bytes) and thesame as the width of the memory data bus DQ[31:0].

[0094] In the case where CONF[3:0] is “0”, an address is generatedaccording to whether a command is issued or not. When issuing an activecommand (ACTISS =1), for example, the ADR[11:10] is selected from theaccess addresses [25:2] as a bank address BADR[1:0] and the ADR[23:12]is selected as a row address A[11:0]. In this case, the most significantbit RA[12:0] becomes 0. Further, as to the row or column addressMADR[12:0], the row address ADR[23:12] is selected, of which the mostsignificant bit is 0. In the case where the advance precharge command isissued (PPREISS=1), on the other hand, ADR[11:0]+1 is selected as thebank address BADR[1:0]. Specifically, an address of a bank adjacent tothe bank designated by the active command is output. In the case wherethe all-precharge command is issued (PALLISS=1), on the other hand, thesame bank address as at the time of issue of an active command isgenerated, while at the time of issuing PPREISS or PALLISS, on the otherhand, the column address ADR[9:2] is generated for selecting specificdata (bytes) in the page as the MADR[12:0].

[0095]FIG. 13 shows a configuration of the bank status management unit121. The bank status management unit 121 includes bank n statusmanagement sections 122 a, 122 b, 122 c, 122 d for holding the status ofthe four banks 0 to 3, respectively. Each bank n status managementsection has the same configuration, and therefore the bank 0 statusmanagement section 122 a will be explained. The bank 0 status-managementsection 122 a includes a coincidence detection circuit 130 a fordetermining whether the bank to be accessed is bank 0 or not, ORcircuits 131 a, 134 a, AND circuits 132 a, 133 a, a mode register 135 a,a row. address buffer 136 a for holding a row address of a pageactivated in the bank 0, an active flag 137 a for indicating that anyone of the pages of the bank 0 is activated, a RAS counter 138 a forcounting the minimum number of-cycles in the process from activation toprecharge, and a RP counter 139 a for counting the minimum number ofcycles in the process from precharge to activation. The row addressbuffer 136 a is connected to a selector 123, the active flag 137 a isconnected to a selector 124, the RAS counter 138 a is connected to aselector 125 and an AND circuit 126, and the RP counter 139 a isconnected to a selector 127. The selectors 123, 124, 125, 127 areadapted to select and output only the signal from the bank statusmanagement unit designated by the bank address.

[0096] The mode register 135 a is for setting the minimum number ofcycles in the process from activation to precharge and the minimumnumber of cycles in the process from precharge to activation. Thesetting is obtained as an arbitrary value through the register busREGBUS.

[0097] The coincidence detection circuit 130 a outputs a high-levelsignal “1” when the bank 0 is designated by the bank address. The ANDcircuit 132 a outputs a high-level signal “1” to the row address buffer136 a, the active flag 137 a and the RAS counter 138 a when ACTISSassumes “1” with the issue of the active command. The AND circuit 133 a,on the other hand, outputs a high-level signal “1” to the OR circuit 134a when the bank 0 is designated by the bank address and any one of thecommands assumes “1” with the issue of PREISS or PPREISS. The OR circuit134 a outputs a reset signal of high level “1” to the active flag 137 aand a start signal of high level “1” to the RP counter 139 a when ahigh-level signal “1” is output from the AND circuit 133 a or PALISSassumes “1”, i.e. on condition that the precharge has been performed.

[0098] The row address buffer 136 a holds the row address RA[12:0] whenthe active command is issued (when ACTISS is asserted) in the accesscycle to the bank 0. In each subsequent access cycle when the same bankis to be accessed, the row address buffer 136 a compares the row addressheld therein with the row address of the same bank to be accessed, andin the case where they coincide with each other, asserts the page hitPHITO and outputs a high-level signal “1” to the selector 123.Specifically, the row address buffer 136 a has the function ofdetermining a page hit. Further, the row address buffer 136 a, togetherwith the selector 123, is configured as page hit determining means fordetermining whether the page to be accessed is active or not.

[0099] When an active command is issued (when ACTISS is asserted) in theaccess cycle to the bank 0, the active flag 137 a is set to “1” therebyto assert the bank active signal BACTO while at the same time outputtinga high-level signal “1” to the selector 124. When a precharge commandfor the bank 0 is issued (when any one of the commands PREISS, PPREISSand PALLISS is asserted), on the other hand, the active flag 137 a iscleared to “0” thereby to negate the signal PACTO (outputs a low-levelsignal “0”). Specifically, the active flag 137 a, together with theselector 124, makes up bank activation determining means for determiningwhether the bank to be accessed is activated or not.

[0100] The RAS counter 138 a, which normally asserts IRASO, startscounting and negates the IRASO when an active command is issued (whenACTISS is asserted) in access cycle to the bank 0, and after passing theminimum number of cycles in the process from activation to precharge setin the mode register 135 a, asserts IRASO again and outputs a high-levelsignal “1” to the selector 125 and the AND circuit 126. Specifically,the RAS counter 138 a, together with the selector 125, makes up meansfor determining the minimum number of cycles in the process fromactivation to precharge.

[0101] The RP counter 139 a, which normally asserts IRP, starts countingwhile at the same negating the IRPO and outputs a low-level signal “0”to the selector 127 when a precharge command for the bank 0 is issued(when any one of the commands PREISS, PPREISS and PALLISS is asserted),and after the passage of the minimum number of cycles in the processfrom precharge to activation set in the mode register 135 a, asserts theIRPO again and outputs a high-level signal “1” to the selector 127.Specifically, the IRP counter 139 a, together with the selector 127,makes up means for determining the minimum number of cycles in theprocess from precharge to activation.

[0102] In the bank status management unit 121 having the configurationmentioned above, assume that the bank activation determining meansdetermines that the bank to be accessed is not activated (in the casewhere the active flag 137 a is “0”). The page to be accessed isactivated on condition that the affirmative result is output from theprecharge-to-activation minimum cycle number determining means (when theoutput of the RP counter 139 a is “1”), and after this activation,information is generated for instructing the memory 7 to execute theaccess by the write or read operation. On the other hand, assumes thatthe bank activation determining means determines that the bank to beaccessed is activated (when the output of the active flag 137 a is “1”).Immediately after the page hit determining means produces an affirmativeresult (when the output of the row address buffer 136 a is “1”), theinformation is generated for giving an instruction to make access by thewrite or read operation. Further, in the case where the bank activationdetermining means determines that the bank to be accessed is activatedand the page hit determining means produces a negative result (when theoutput of the row address buffer 136 a is “0”), the bank to be accessedis precharged on condition that the activation-to-precharge minimumcycle number determining means produces an affirmative result (when theoutput of the RAS counter 139 a is “1”). Then, after activating the pagenext to be accessed, the information is generated for giving aninstruction to execute the access by the write or read operation. Theseinformation are output to the memory control unit 11.

[0103] Now, the memory control unit 11 will be specifically describedwith reference to FIGS. 14 to 19. The memory control unit 11, as shownin FIG. 14, includes a command generating unit 110, a DQM generatingunit 111, a read data control-unit 112, and latches 113, 114, 115, 116.

[0104] The command generating unit 110, upon receipt of signals for CL2,RDY, WR, DEVSEL[3:0] from the access arbiter 10, generates variouscommands for accessing the memory 7 based on these signals, and outputsthe various commands to the bank management and address generating unit12. At the same time, the command generating unit 110 outputs controlsignals (RAS#, CAS#, WE#, CS#) corresponding to the commands to thememory 7 thereby to control the access to the memory 7.

[0105]FIG. 15 shows the status transition for controlling the commandissue in the command generating unit 110, FIG. 16 the conditions foreach status transition in FIG. 15, and FIG. 17 the status of the outputsignal due to the status transition (the state of the control signalcorresponding to each command) in FIG. 15.

[0106] Reference is made to FIG. 15. In IDLE state 1100, no accessrequest is given from the devices and an access request waiting cycleprevails. Once the transition condition is met that the RDY signal isoutput in the absence of the IRP output (#a in FIG. 16), the process isexecuted for activation as a transition destination. The ACTV status1101 is a cycle for issuing the bank activation command (ACTV). Oncondition that the advance precharge is asserted (#c of FIG. 16), thestatus is transferred to PRE-A. In the case where the advance prechargeis negated and two or three cycles are designated as RCD2 (#d of FIG.16), on the other hand, the status transfers to WAIT-B. Otherwise (#6 ofFIG. 16), the status transfers to WAIT-A. The WAIT-A status 1102 is thewait cycle (one-cycle wait cycle) between ACTV and WRITE or between ACTVand READ for the column latency of 3 cycles, while the WAIT-B status1103 is a wait cycle (one-cycle wait cycle) before issue of a writecommand or a read command. The PRE-A status 1104 is a cycle for issuing,in the transaction of the advance precharge mode upon assertion of theadvance precharge PDEV, a precharge command (PRE) for the adjacent bankn+1 immediately after issuing the active command ACTV to the bank n. TheWRITE status 1105 is a cycle for issuing a write command (WRITE), theREAD status 1106 is a cycle for issuing a read command (READ), theWAIT-C status 1107 is a wait cycle (one cycle) before issuing theprecharge command or the all-bank precharge command, the PRE-B status1108 is a cycle for issuing a precharge command (PRE), and the PALLstatus 1109 is a cycle for issuing the all-bank precharge command(PALL). Specifically, in each status, a command is issued for transferto a transition destination when the transition conditions are met. Theterm “otherwise” indicates a common practice, and indicates that in thecase where the source and destination are the same, the same processingis repeated.

[0107] Upon generation of various commands in the memory control unit11, whether a command has been issued or not is indicated by “1” and“0”. In the case where no command is issued, the output value is at lowlevel of “0”, while when the command is issued, the output value assumesa high level of “1”. The commands ACTISS, PREISS, PPREISS, PALLISS,WRITE and READ are asserted in the case where the next clock cycleassumes the ACTV status, the PRE-B status, the PRE-A status, the PALLstatus, the WRITE status and the READ status, respectively. Upon issueof various commands, a control signal corresponding to a given commandsignal is output to the memory 7 as a negative logic signal.

[0108] In the case where the active command ACTV is issued, for example,the signals CS# of “0”, RAS# of “0”, CAS# of “1” and WE# of “1” areoutput to the memory 7 as a control signal. Also, when an advanceprecharge command (PRE-A) is issued, the control signals including CS#of “0”, RAS# of “0”, CAS# of “1” and WE# of “0” are output to the memory7 as a negative logic signal. These control signals correspond to thecommands, respectively, so that the memory 7 can be controlled based onthe commands.

[0109] The DQM generating unit 111 is supplied with a byte enable signalBE[3:0] for designating the bytes to be written. Based on the byteenable signal BE, as shown in FIG. 18, the DQM generating unit 111outputs a signal “0” only for the bytes to be written when WRITEISS isissued from the command generating unit 110, and a mask signal dqm[3:0]of “1” for the bytes of which the write operation is inhibited.Specifically, when WRITEISS is asserted and the WRITE command is issuedin the next cycle, the polarity inverted signal of the byte enablesignal BE[3:0] is output as dqm[3:0]. Otherwise, the signal is negatedto low level. The signal dqm[3:0] is latched by the latch 117 and outputto the memory 7 as DQM[3:0].

[0110] The read data control unit 112, as shown in FIG. 19, includeslatches 1120, 1121, 1222, 1123, 1124, a read data strobe signal (RSTBi)generating circuit (RSTBGEN) 1125, a read data set signal (DQSET)generating circuit (DQSETGEN) 1126, a DQ output enable signal (OUTENB)generating circuit (OUTENBGEN) 1127.

[0111] The latches 1120, 1121, 1122, 1123, 1124 are adapted to latch theREADISS and the DEVSEL[3:0] sequentially in synchronism with the clockcycle. This is accomplished in such a manner that RSTBi, DQSET andOUTENB are generated at the timing of output of the read data by thememory 7 with a column latency from the issue of the read command.

[0112] The read data strobe signal generating circuit 1125 retrieves theread data received from the memory 7 and outputs it to the devices asRDT[31:0]. At the same time, the circuit 1125 asserts RSTBi for thedevice indicated by DEVD5[3:0] in the case where CL2 is 0 (columnlatency is three cycles) and RSTBD5 is asserted on the one hand, andasserts RSTBi for the device indicated by DEVD4[3:0] in the case whereCL2 is 1 (column latency is two cycles) and RSTBD4 is asserted on theother hand.

[0113] Specifically, the read data strobe signal generating circuit 1125is configured to generate the read data strobe signal RSTBi inaccordance with the equations below.

RSTBa=CL 2 & RSTBD 4 & (DEVD 4=DEVa)|CL 2 & RSTBD 4 & (DEVD 5=DEVa)

RSTBb=CL 2 & RSTBD 4 & (DEVD 4=DEVb)|CL 2 & RSTBD 4 & (DEVD 5=DEVb)

. . .

RSTBe=CL 2 & RSTBD 4 & (DEVD 4=DEVe)|CL 2 & RSTBD 4 & (DEVD 5=DEVe)

[0114] where “&” designates a logic product, and “|” a logic sum.

[0115] The read data set signal generating circuit 1126 holds the latchof the data control unit 15 by asserting DQSET as soon as the memory 7outputs the read data. For this purpose, the read data set signalgenerating circuit 1126 asserts DQSET upon assertion of RSTBD4 in thecase where CL2 is 0 (the column latency is three cycles) and assertsDQSET upon assertion of RSTBD3 in the case where CL2 is 1 (the columnlatency is two cycles).

[0116] Specifically, the read data set signal generating circuit 1126 isconfigured to generate a read data set signal in accordance with theequation below.

DQSET=CL 2 & RSTD 3|({overscore ( )}CL 2 & RSTBD 4)

[0117] where “{overscore ( )}” indicates inversion.

[0118] The DQ output enable signal generating circuit 1127 suppressesthe output of DQ[31:0] by the memory controller 1 not only in the clockcycle for the memory 7 to output the read data but also during theperiod from one clock cycle before the memory 7 outputs the read data toone clock cycle after the memory 7 outputs the read data. For thispurpose, the enable signal OUTENB (one clock cycle earlier than theDQ[31:0] output since latched temporarily by the data control unit 15)of the DQ[31:0] output drive of the data control unit 15 is negated fromone clock cycle before the memory 7 outputs the read data to one clockafter the memory 7 outputs the read data, and asserted otherwise.Specifically, OUTENB is asserted upon assertion of RSTBD3 or RSTBD4 inthe case where CL2 is 0 (the column latency is 3 cycles), while OUTENBis asserted upon assertion of RSTBD1, RSTBD2 or RSTBD3 in the case whereCL2 is 1 (the column latency is 3 cycles).

[0119] Specifically, the DQ output enable signal generating circuit 1127is configured to generate the DQ output enable signal in accordance withthe following equations:

OUTENB={overscore ( )}(CL 2 & (RSTBD 1|RSTBD 2|RSTBD 3)

|{overscore ( )}(CL 2 & (RSTBD 2|RSTBD 3|RSTBD 4)

[0120] On the other hand, the data control unit 15, as shown in FIG. 20,includes a latch 150 for latching the data output enable signal OUTENB,a latch 151 for latching the write data WDT[31:0], a latch 152 forholding, during assertion of the DQ set signal, the read data DQ[31:0]output by the memory 7, an output buffer 153 to DQ[31:0] and an inputbuffer 154 from DQ[31:0].

[0121] The latch 150 latches the data output enable signal OUTENB andoutputs an inverted polarity signal OUTENB#. The output buffer 153outputs the write data WDT[31:0] latched in the latch 151 to DQ[31:0]when OUTENB# is at low level. The latch 152, on the other hand, holdsthe read data DQ[31:0] output from the memory 7 when DQSET is assertedand outputs it to all the devices as RDTi[31:0]. Since the read datastrobe signal RSTBi is asserted only for one device, only one deviceretrieves the read data.

[0122] Now, the memory access operation by the memory controller 1 willbe explained with reference to FIGS. 21 and 22. The processing free ofadvance precharge will be explained with reference to FIG. 21, and theprocessing with advance precharge with reference to FIG. 22. The signalRCD2 is assumed to be “1” (RAS-CAS latency: 2 cycles), and CL2 to be “0”(column latency: 3 cycles).

[0123] In FIG. 21, in the absence of advance precharge, PDa is set tolow level. The memory controller 1, upon detection of the assertion ofthe ready signal RDYa from the device a at clock cycle T0, issues anACTV command at clock cycle T1, asserts the acknowledge signal ACKa forthe first access cycle a0 at clock cycle T2, and issues a READ commandat clock cycle T3. At the same time, the bank address b0 for designatingthe bank 0 and the row address ra0 for designating a specific page inbank 0 are generated, and the processing is executed for activating thepage designated for access by the row address ra0 of the bank 0.Further, with the issue of the READ command, the column address ca0 isoutput for reading the designated data (bytes) of the activated page,and the access for reading the designated data is carried out at clockcycle T3.

[0124] After that, in the case where the read access for the same pageis continued, the acknowledge signal ACKa for the second access cycle a1is asserted at clock cycle T3, and the READ command is issued at clockcycle T4. Also, the acknowledge signal ACKa for the third access cyclea2 is asserted at clock cycle T4, and the READ command is issued atclock cycle T5. As a result, the data designated by the column addressesca0, ca1, ca2 are sequentially read as read data rda0, rda1, rda2,respectively.

[0125] Upon occurrence of a page mishit (in the case where a pagedifferent from the page designated at row address ra0 is accessed) atthe fourth access cycle a3 while the read access for the same page iscontinued, the acknowledge signal ACKa is temporarily negated at andafter clock cycle T5, the PRE command is issued from the memory controlunit 11 at clock cycle T6, and the bank address b1 for selecting bank 1is output. After one clock cycle, the ACTV command is issued to set thebank 1 as an object to be accessed at clock cycle T8, and a row addressra1 for selecting the designated page of bank 1 is output. As a result,the page designated by the row address ra1 is activated. After assertionof the acknowledge signal ACKa at clock cycle T9, the READ command isissued at clock cycle T10. As a result, the column addresses ca3, ca4are output sequentially for selecting the designated data of the pageassociated with the bank 1 and designated by the row address ra1. Thus,the read data rda3, rda4 are sequentially read at clock cycles T12, T13,and in accordance with the read data strobe signal RSTBa, the read datarda3, rda4 are sequentially transferred to the devices.

[0126] The read data rda0 for the first access cycle a0 is output fromthe memory 7 at clock cycle T5, and upon assertion of the read datastrobe signal RSTBa by the memory controller 1 at clock cycle T6, theread data RDTa[31:0] is output to the device a.

[0127] In a similar fashion, the read data RDTa[31:0] for the second,third, fourth and fifth access cycles a1, a2, a3 and a4 are output tothe devices upon assertion of the read data strobe signal RSTBa at clockcycles T7, T8, T13 and T14, respectively. In this case, the readtransaction is 4 clock cycles (T6 to T9) delayed by a page mishit.

[0128] Assume, on the other hand, that the device a requires the advanceprecharge such as a graphic processing unit and outputs an accessrequest. In view of the fact that the signal PDa indicating the advanceprecharge is asserted, a command for activating the page to be accessedis generated. At the same time, a command is generated for executing theadvance precharge for the page to be accessed next or subsequentlybefore execution of the read or write access to the activated page.

[0129] Specifically, in the case where the device a asserts the readysignal RDYa and the signal PDa at clock cycle T0, the ACTV command isissued at clock cycle T1, and the bank address b0 for selecting bank 0and the row address ra0 for selecting a specific page of bank 0 areoutput. Then, at the next clock cycle T2, the command PRE for theadvance precharge is issued.

[0130] In this case, the advance precharge command, like the normalprecharge command, designates a bank adjacent to the activated bank,which adjacent bank has the same address as the bank activated by theACTV command at clock cycle T1, plus 1. In the case where the bankaddress of the ACTV command is 1 at clock cycle T1, for example, thebank address of the PRE command at clock cycle T2 is 2, and in the casewhere the bank address of the ACTV command at clock cycle T1 is 0, thebank address of the PRE command at clock cycle T2 is 1. Similarly, inthe case where the bank address of the ACTV command at clock cycle T1 is3, the bank address of the PRE command at clock cycle T2 is 0.

[0131] Assume that the bank designated by the bank address b1 isprecharged (since the data of the page that has already been transferredto the sense amplifier is known from the preceding process to belong towhich page of which bank, the processing is executed for returning tothe original page the data that has already been transferred to thesense amplifier). The READ command is issued at clock cycles T3, T4, T5,and the read access is made to the bytes designated by the columnaddresses ca0, ca1, ca2 in the page designated by the row address ra0 inthe bank designated by the bank address b0.

[0132] After that, if a page mishit occurs at the fourth access cycle a3(in the case where the access over the tile boundary is executed bydrawing), the processing is started for the bank designated by the bankaddress b1 as an object to be accessed. In this case, the precharge ofthe bank designated by the bank address b1 has already been executed atclock cycle T2 and the data of the page belong to the particular bankhas already been returned to the original page. Therefore, the pagebelonging to this bank is immediately activated by issuing the ACTBcommand. After that, in order to read the designated data from the pagewhich-belongs to the bank designated by the bank address b1 and which isdesignated by the row address ra1, the column addresses ca3, ca4 areoutput in accordance with the READ command issued-at the fifth accesscycle a4, and the read access is executed to the data (bytes) designatedby the column addresses ca3 and ca4.

[0133] As described above, since a page mishit occurs as an access ismade over the page boundary, the advance precharge is executed for thebank next to be accessed prior to the occurrence of a mishit. Even inthe case where a page mishit occurs at the fourth access cycle a3,therefore, the ACTV command can be issued at clock cycle T6, theacknowledge signal ACKa can be asserted at clock cycle T7 and the READcommand can be issued at clock cycle T8. Thus, the delay of the readtransaction due to the page mishit is two clock cycles (T6 to T7). Ascompared with the case shown in FIG. 21, the execution of the advanceprecharge can reduce the delay of the read transaction, with the resultthat the shortened overhead time increases the data amount accessibleper unit time and can contribute to an improved band width.

[0134] Although the processing in FIGS. 21 and 22 refers to the readtransaction, the delay of the write transaction can also be reduced byexecuting the advance precharge.

[0135] As described above, according to this embodiment, in the tileaddress mapping of image data in the memory 7, the horizontally adjacenttiles are arranged in different banks at the ascending order of bankaddress, and in the case where the image data area read or written, theadvance precharge is executed for the bank address n+1 immediately afteractivating a predetermined page of the bank address n to be accessed.Even in the case a page mishit occurs over the tile boundary whilereading-or writing the image data, therefore, the overhead of the memoryaccess due to a page mishit can be reduced in view of the fact that thebank having arranged therein the tiles next to be accessed is alreadyprecharged.

[0136] Also, according to this embodiment, the memory controller 1, whenselecting a memory access from the devices, selects one device inaccordance with the order of priority. In the case where an access isrequested from a device of higher priority while the access to theselected device is under execution, the particular access in executionis suspended, and the memory access from the device of higher priorityis executed. Even in the case where the access requests from a pluralityof devices contend each other, therefore, an access request is selectedfrom a device in the descending order of real time processingrequirement, and thus the memory 7 can be accessed. As a result, thedelay in the image data access due to the access contention can besuppressed.

[0137] Further, according to this embodiment, in the case where theadvance precharge is not executed, the information of the active flag,the row address buffer RAS counter and the PR counter are referred to,and upon occurrence of a page mishit, the precharge and activation canbe both executed at the shortest timing within the range meeting theactivation-to-precharge minimum cycle number and theprecharge-to-activation minimum cycle number.

1. A memory controller comprising: means for receiving, from aprocessor, a request for access to a dynamic random access memory havinga data storage area divided into a plurality of banks each divided intoa plurality of pages; and memory control means for activating a page tobe accessed, based on said access request from said processor, andexecuting, before a next request for access to a page to be accessedsubsequently by said processor, precharge of said page to be accessedsubsequently.
 2. A memory controller comprising: means for receiving,from a processor, a request for access to a dynamic random access memoryhaving a data storage area divided into a plurality of banks eachdivided into a plurality of pages; and memory control means foractivating a page to be accessed, based on said access request from saidprocessor, and executing, before a next request for access to a page tobe accessed subsequently by said processor, precharge of a bankcorresponding to said page to be accessed subsequently.
 3. A memorycontroller for use with a processor and a dynamic random access memory,comprising: a terminal for receiving a request for access from saidprocessor to a dynamic random access memory having a data storage areadivided into a plurality of banks each divided into a plurality ofpages; and memory control means for issuing an active command foractivating a page to be accessed, based on said access request from saidprocessor, and issuing a precharge command for executing, before a nextrequest for access to a page to be accessed subsequently, precharge ofsaid page to be accessed subsequently.
 4. A memory controller for usewith a processor and a dynamic random access memory, comprising: aterminal for receiving a request for access from said processor to adynamic random access memory having a data storage area divided into aplurality of banks each divided into a plurality of pages; and memorycontrol means for issuing an active command for activating a page to beaccessed, based on said access request from said processor, and issuinga precharge command for executing, before a next request for access to apage to be accessed subsequently, precharge of a bank corresponding tosaid page to be accessed subsequently.
 5. A memory controllercomprising: a terminal for receive, from a processor, a request foraccess to a dynamic random access memory having a data storage areadivided into a plurality of banks each divided into a plurality ofpages; and a memory control unit to activate a page to be accessed,based on said access request from said processor, and to execute, beforea next request for access to a page to be accessed subsequently by saidprocessor, precharge of said page to be accessed subsequently.